Jose Angel Diaz Madrid

About

I obtained a degree in Automation and Industrial Electronics Engineering from the Polytechnic University of Cartagena, graduating in 2000. My academic journey included a master's thesis (TFM) focused on microelectronic design, which laid a solid foundation for a dynamic career in research and technology transfer within the European microelectronics industry. In 2001, I began my professional career as a Mixed-Signal IC Engineer during an internship at the Fraunhofer Institute IIS Research Center, supported by a Leonardo Scholarship. Over the following eight years, I contributed to groundbreaking European research projects, fostering long-term engagement with innovative developments in the field. Additionally, I played a key role in establishing a strong collaborative relationship between the Polytechnic University of Cartagena and the Fraunhofer Institute through partnership agreements. In 2009, I concluded my professional relationship with the Fraunhofer Institute, although I maintained ongoing research collaboration with the organization. That same year, I returned to Spain and joined Bionet Servicios Técnicos S.L., where I held various leadership roles as an Engineering Coordinator in Automation until 2017. At Bionet, I leveraged my expertise in technology transfer and systems engineering to enhance technical operations and drive innovation in biotechnological industrial applications. Today, Bionet is recognized as a leading company in the development of biotechnological reactors for various industries. During my tenure at both the Fraunhofer Institute and Bionet, I contributed to several competitive research projects in Spain at the regional level (03094/PI/05, 08801/PI/08, 15303/PI/10) and national level (TIN2006-15460-C04-04, TEC2012-38921-C02-0, TEC2015-66878-C3-2-R), as well as technology transfer projects in Germany (PROFCAM, 2004, and TSDK, 2004). In 2017, I completed my doctoral studies, which focused on the modeling, design, and implementation of high-performance, low-power dissipation pipeline analog-to-digital converters. Following this, I transitioned to academia, taking on teaching responsibilities as an Associate Professor at both the Polytechnic University of Cartagena (UPCT) and the Defense University Center (CUD-UPCT), part of the Spanish Air and Space Force. I left Bionet in 2017 to dedicate myself fully to my academic career at the Defense University Center in San Javier. Since then, I have advanced through various full-time faculty positions, maintaining an active role in competitive research projects led by UPCT, such as RTI2018-097088-B-C33 and PID2021-128009OB-C33. In all these projects, I was able to transfer much of the knowledge acquired during my years at the Fraunhofer Institute IIS in the design of mixed-signal ICs. Within this framework of collaboration, I completed a three-month postdoctoral research stay in 2019 at the Advanced Analog Circuits department of this institute, further strengthening my expertise in this area. In 2022, I participated in a regional technology transfer project within the Regional Program for Support of Knowledge Transfer, Valorization, and Scientific Entrepreneurship of the Fundación Séneca, focused on proof-of-concept development (21084/PDC/19). This project, led by Professor Pía López Jornet and conducted in collaboration with the University of Murcia's Faculty of Dentistry, aimed to improve outcomes for patients suffering from xerostomia. It culminated in the development of a utility model (Nº: ES263049). Finally, I have also assumed significant institutional responsibilities, serving as the Coordinator of External Internships since 2019 and, beginning in 2025, as the Secretary of the Department of Technology and Aerospace Sciences at CUD-UPCT.

Work

Centro Universitario de la Defensa
|

Profesor Permantente Laboral (Associate Profesor)

Spain

Centro Universitario de la Defensa
|

Profesor Permantente Laboral (Associate Profesor)

Spain

Centro Universitario de la Defensa
|

Profesor Contratado Doctor (Associate Profesor)

Spain

Centro Universitario de la Defensa
|

Profesor Contratado Doctor (Associate Profesor)

Spain

Centro Universitario de la Defensa
|

Profesor Ayudante Doctor

Spain

Centro Universitario de la Defensa
|

Profesor Ayudante Doctor

Spain

Bionet
|

Coordinador del Departamento

Spain

Bionet
|

Coordinador del Departamento

Spain

Centro Universitario de la Defensa
|

Profesor Asociado

Spain

Centro Universitario de la Defensa
|

Profesor Asociado

Spain

Centro Universitario de la Defensa
|

Profesor Asociado

Spain

Centro Universitario de la Defensa
|

Profesor Asociado

Spain

Universidad Politécnica de Cartagena
|

Profesor Asociado

Spain

Universidad Politécnica de Cartagena
|

Profesor Asociado

Spain

Universidad Politécnica de Cartagena
|

Profesor Asociado

Spain

Universidad Politécnica de Cartagena
|

Profesor Asociado

Spain

Fraunhofer IIS
|

Ingeniero de Diseño Analógico y en Modo Mixto

Germany

Fraunhofer IIS
|

Ingeniero de Diseño Analógico y en Modo Mixto

Germany

Fraunhofer IIS
|

Doctorando

Germany

Fraunhofer IIS
|

Doctorando

Germany

Fraunhofer IIS
|

Doctorando

Germany

Fraunhofer IIS
|

Doctorando

Germany

Fraunhofer IIS
|

Ingeniero de Diseño Analógico y en Modo Mixto

Germany

Fraunhofer IIS
|

Ingeniero de Diseño Analógico y en Modo Mixto

Germany

Fraunhofer IIS
|

Ingeniero de Diseño Analógico y en Modo Mixto

Germany

Fraunhofer IIS
|

Ingeniero de Diseño Analógico y en Modo Mixto

Germany

Fraunhofer IIS
|

Practicante

Germany

Fraunhofer IIS
|

Practicante

Germany

Education

Universidad Politécnica de Cartagena
Spain

Doctor por la Universidad Politécnica de Cartagena

Universidad Politécnica de Cartagena
Spain

Doctor por la Universidad Politécnica de Cartagena

Universidad Politécnica de Cartagena
Spain

Ingeniero en Automática y Electrónica Industrial

Universidad Politécnica de Cartagena
Spain

Ingeniero en Automática y Electrónica Industrial

Universidad de Murcia
Spain

Ingeniero Técnico Industrial (Esp. Electricidad)

Universidad de Murcia
Spain

Ingeniero Técnico Industrial (Esp. Electricidad)

Publications

Improvement of ANNs Performance to Generate Fitting Surfaces for Analog CMOS Circuits

Published by

Lecture Notes in Computer Science

Summary

book-chapter

Improvement of ANNs Performance to Generate Fitting Surfaces for Analog CMOS Circuits

Published by

Lecture Notes in Computer Science

Summary

book-chapter

Interlaced 6T-10T CMOS in-memory computing circuit for low silicon area pipelined DNNs

Published by

2025 IEEE International Symposium on Circuits and Systems (ISCAS)

Summary

conference-paper

Optimizing binary neural network quantization for fixed pattern noise robustness

Published by

Scientific Reports

Summary

journal-article

Interlaced 6T-10T CMOS in-memory computing circuit for low silicon area pipelined DNNs

Published by

2025 IEEE International Symposium on Circuits and Systems (ISCAS)

Summary

conference-paper

Optimizing binary neural network quantization for fixed pattern noise robustness

Published by

Scientific Reports

Summary

journal-article

CMOS Pipelined in-Memory Computing Circuit for Column-Wise Image Sensor Architectures

Published by

2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS)

Summary

conference-paper

CMOS Pipelined in-Memory Computing Circuit for Column-Wise Image Sensor Architectures

Published by

2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS)

Summary

conference-paper

A real-time and energy-efficient SRAM with mixed-signal in-memory computing near CMOS sensors

Published by

Journal of Real-Time Image Processing

Summary

journal-article

A real-time and energy-efficient SRAM with mixed-signal in-memory computing near CMOS sensors

Published by

Journal of Real-Time Image Processing

Summary

journal-article

A 12T SRAM in-Memory Computing differential current architecture for CNN implementations

Published by

2023 IEEE International Symposium on Circuits and Systems (ISCAS)

Summary

conference-paper

A 12T SRAM in-Memory Computing differential current architecture for CNN implementations

Published by

2023 IEEE International Symposium on Circuits and Systems (ISCAS)

Summary

conference-paper

A 12T SRAM in-Memory Computing differential current architecture for CNN implementations

Published by

2023 IEEE International Symposium on Circuits and Systems (ISCAS)

Summary

conference-paper

A 12T SRAM in-Memory Computing differential current architecture for CNN implementations

Published by

2023 IEEE International Symposium on Circuits and Systems (ISCAS)

Summary

conference-paper

Students” perceptions of key competencies supporting work-integrated learning

Published by

International Journal of Engineering Education

Summary

journal-article

Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC

Published by

Circuits, Systems, and Signal Processing

Summary

journal-article

Students” perceptions of key competencies supporting work-integrated learning

Published by

International Journal of Engineering Education

Summary

journal-article

Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC

Published by

Circuits, Systems, and Signal Processing

Summary

journal-article

Low power 9-bit 500 kS/s 2-stage cyclic ADC using OTA variable bias current

Published by

Analog Integrated Circuits and Signal Processing

Summary

journal-article

Mixed Signal Multiply and Adder Parallel Circuit for Deep Learning Convolution Operations

Published by

2020 IEEE International Symposium on Circuits and Systems (ISCAS)

Summary

conference-paper

All-hardware SIFT implementation for real-time VGA images feature extraction

Published by

Journal of Real-Time Image Processing

Summary

journal-article

All-hardware SIFT implementation for real-time VGA images feature extraction

Published by

Journal of Real-Time Image Processing

Summary

journal-article

All-hardware SIFT implementation for real-time VGA images feature extraction

Published by

Journal of Real-Time Image Processing

Summary

journal-article

All-hardware SIFT implementation for real-time VGA images feature extraction

Published by

Journal of Real-Time Image Processing

Summary

journal-article

Mixed Signal Multiply and Adder Parallel Circuit for Deep Learning Convolution Operations

Published by

2020 IEEE International Symposium on Circuits and Systems (ISCAS)

Summary

conference-paper

Low power 9-bit 500 kS/s 2-stage cyclic ADC using OTA variable bias current

Published by

Analog Integrated Circuits and Signal Processing

Summary

journal-article

Las prácticas externas como herramienta para el análisis de las competencias del Grado en Ingeniería en Organización Industrial del CUD de San Javier

Published by

VIII congreso internacional multidisciplinar de investigación educativa

Summary

conference-paper

A low kickback fully differential dynamic comparator for pipeline analog‐to‐digital converters

Published by

Engineering Reports

Summary

journal-article

Las prácticas externas como herramienta para el análisis de las competencias del Grado en Ingeniería en Organización Industrial del CUD de San Javier

Published by

VIII congreso internacional multidisciplinar de investigación educativa

Summary

conference-paper

A low kickback fully differential dynamic comparator for pipeline analog‐to‐digital converters

Published by

Engineering Reports

Summary

journal-article

Análisis de las competencias del Grado en Ingeniería de Organización Industrial del CUD de San Javier a través de las prácticas externas

Published by

Certiuni Journal

Summary

journal-article

An all‐hardware implementation of the subpixel refinement stage in <scp>SIFT</scp> algorithm

Published by

International Journal of Circuit Theory and Applications

Summary

journal-article

Implementación en fpga (field-programmable gate array) del algoritmo sift para la extracción de puntos característicos de imágenes vga (video graphics array) en tiempo real

Published by

VI Congreso Nacional de i+d en Defensa y Seguridad

Summary

conference-paper

An all‐hardware implementation of the subpixel refinement stage in <scp>SIFT</scp> algorithm

Published by

International Journal of Circuit Theory and Applications

Summary

journal-article

Implementación en fpga (field-programmable gate array) del algoritmo sift para la extracción de puntos característicos de imágenes vga (video graphics array) en tiempo real

Published by

VI Congreso Nacional de i+d en Defensa y Seguridad

Summary

conference-paper

Análisis de las competencias del Grado en Ingeniería de Organización Industrial del CUD de San Javier a través de las prácticas externas

Published by

Certiuni Journal

Summary

journal-article

FPGA synthesis of an stereo image matching architecture for autonomous mobile robots

Published by

2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS)

Summary

conference-paper

FPGA synthesis of an stereo image matching architecture for autonomous mobile robots

Published by

2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS)

Summary

conference-paper

An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation

Published by

2017 IEEE International Symposium on Circuits and Systems (ISCAS)

Summary

conference-paper

FPGA synthesis of an stereo image matching architecture for autonomous mobile robots

Published by

2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS)

Summary

conference-paper

FPGA synthesis of an stereo image matching architecture for autonomous mobile robots

Published by

2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS)

Summary

conference-paper

An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation

Published by

2017 IEEE International Symposium on Circuits and Systems (ISCAS)

Summary

conference-paper

A reconfigurable two-stage cyclic ADC for low-power applications in 3.3 V 0.35 µm CMOS

Published by

International Journal of Electronics

Summary

journal-article

ES1263049: Dispositivo para la estimulación salival

Summary

registered-copyright

Técnicas para la reducción del consumo en ADCs de topología pipeline

Published by

IV Congreso Nacional de i+d en Defensa y Seguridad DESEi+d 2016

Summary

journal-article

ES1263049: Dispositivo para la estimulación salival

Summary

registered-copyright

Técnicas para la reducción del consumo en ADCs de topología pipeline

Published by

IV Congreso Nacional de i+d en Defensa y Seguridad DESEi+d 2016

Summary

journal-article

A reconfigurable two-stage cyclic ADC for low-power applications in 3.3 V 0.35 µm CMOS

Published by

International Journal of Electronics

Summary

journal-article

Low-Frequency CMOS Bandpass Filter for PIR Sensors in Wireless Sensor Nodes

Published by

IEEE Sensors Journal

Summary

journal-article

Low-Frequency CMOS Bandpass Filter for PIR Sensors in Wireless Sensor Nodes

Published by

IEEE Sensors Journal

Summary

journal-article

Implementación de un ADC de tipo cíclico y topología pipeline, reconfigurable y de bajo consumo en tecnología CMOS de 0.35um

Published by

Congreso nacional de I+D en Defensa y Seguridad (DESEi+d 2013)

Summary

conference-proceedings

Synthesis of CMOS analog circuit VHDL‐AMS descriptions using parameterizable macromodels

Published by

International Journal of Circuit Theory and Applications

Summary

journal-article

Implementación de un ADC de tipo cíclico y topología pipeline, reconfigurable y de bajo consumo en tecnología CMOS de 0.35um

Published by

Congreso nacional de I+D en Defensa y Seguridad (DESEi+d 2013)

Summary

conference-proceedings

Synthesis of CMOS analog circuit VHDL‐AMS descriptions using parameterizable macromodels

Published by

International Journal of Circuit Theory and Applications

Summary

journal-article

Fuzzy logic technique for accurate analog circuits macromodel sizing

Published by

International Journal of Circuit Theory and Applications

Summary

journal-article

Fuzzy logic technique for accurate analog circuits macromodel sizing

Published by

International Journal of Circuit Theory and Applications

Summary

journal-article

Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing

Published by

2009 Design, Automation &amp; Test in Europe Conference &amp; Exhibition

Summary

conference-paper

Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing

Published by

2009 Design, Automation &amp; Test in Europe Conference &amp; Exhibition

Summary

conference-paper

VHDL-AMS description of a Biosignal monitor integrated circuit

Published by

XXIV Conference on Design of Circuits and Integrated Systems

Summary

conference-paper

Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing

Published by

2009 Design, Automation &amp; Test in Europe Conference &amp; Exhibition

Summary

conference-paper

VHDL-AMS description of a Biosignal monitor integrated circuit

Published by

XXIV Conference on Design of Circuits and Integrated Systems

Summary

conference-paper

Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing

Published by

2009 Design, Automation &amp; Test in Europe Conference &amp; Exhibition

Summary

conference-paper

Comparative analysis of two operational amplifier topologies for a 40MS/s 12-bit pipelined ADC in 0.35&amp;#x03BC;m CMOS

Published by

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial

Summary

conference-paper

Comparative analysis of two operational amplifier topologies for a 40MS/s 12-bit pipelined ADC in 0.35&amp;#x03BC;m CMOS

Published by

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial

Summary

conference-paper

Comparative analysis of two operational amplifier topologies for a 40MS/s 12-bit pipelined ADC in 0.35&amp;#x03BC;m CMOS

Published by

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial

Summary

conference-paper

Accurate and reusable macromodeling technique using a fuzzy-logic approach

Published by

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

Summary

conference-paper

Accurate and reusable macromodeling technique using a fuzzy-logic approach

Published by

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

Summary

conference-paper

Comparative analysis of two operational amplifier topologies for a 40MS/s 12-bit pipelined ADC in 0.35&amp;#x03BC;m CMOS

Published by

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial

Summary

conference-paper

Parametrizable VHDL-AMS model of a transconductance amplifier

Published by

XXII Conference on Design of Circuits and Integrated System

Summary

conference-paper

Evaluation of VHDL-AMS models of a high performance ADC

Published by

2007 IEEE International Symposium on Industrial Electronics

Summary

conference-paper

Evaluation of VHDL-AMS models of a high performance ADC

Published by

2007 IEEE International Symposium on Industrial Electronics

Summary

conference-paper

Parametrizable VHDL-AMS model of a transconductance amplifier

Published by

XXII Conference on Design of Circuits and Integrated System

Summary

conference-paper

Evaluation of VHDL-AMS models of a high performance ADC

Published by

2007 IEEE International Symposium on Industrial Electronics

Summary

conference-paper

Evaluation of VHDL-AMS models of a high performance ADC

Published by

2007 IEEE International Symposium on Industrial Electronics

Summary

conference-paper

VHDL-AMD Model Of A 40M/s 12 Bits Pipeline ADC

Published by

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.

Summary

conference-paper

VHDL-AMD Model Of A 40M/s 12 Bits Pipeline ADC

Published by

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.

Summary

conference-paper

VHDL-AMD Model Of A 40M/s 12 Bits Pipeline ADC

Published by

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.

Summary

conference-paper

VHDL-AMD Model Of A 40M/s 12 Bits Pipeline ADC

Published by

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.

Summary

conference-paper

Current mode CMOS synthesis of a motor–control neural system

Published by

Lecture Notes in Computer Science

Summary

book-chapter

An analogue current–mode hardware design proposal for preprocessing layers in ART-based neural networks

Published by

Lecture Notes in Computer Science

Summary

book-chapter

CMOS analog implementation of a simplified spinal cord neural model

Published by

SPIE Proceedings

Summary

conference-paper

CMOS analog implementation of a simplified spinal cord neural model

Published by

SPIE Proceedings

Summary

conference-paper

Current-mode implementation of processing modules in ART-based neural networks

Published by

SPIE Proceedings

Summary

conference-paper

Current mode CMOS synthesis of a motor–control neural system

Published by

Lecture Notes in Computer Science

Summary

book-chapter

Current-mode implementation of processing modules in ART-based neural networks

Published by

SPIE Proceedings

Summary

conference-paper

An analogue current–mode hardware design proposal for preprocessing layers in ART-based neural networks

Published by

Lecture Notes in Computer Science

Summary

book-chapter

Jose Angel Diaz Madrid