DR. MYSORE SHIVA

Spearheaded the design of end-to-end power delivery networks for SoC domains, optimizing voltage regulators and on-chip decoupling to significantly enhance system reliability and performance.

Certified cutting-edge EM tools including EMX, Keysight Peakview, and RF-Pro on Intel's 2nm, 1.8nm, and 1.6nm technology nodes, ensuring design accuracy and compliance.

Utilized commercial 2.5D electromagnetic simulators to model and simulate PCBs and packages, extracting N-port models and impedance profiles that informed critical design improvements.

Executed time-domain simulations to analyze supply rail behaviors under worst-case scenarios, identifying and correcting critical droops and overshoots to ensure signal integrity.

Provided expert power integrity guidance to cross-functional hardware design, PCB layout, and system architecture teams, contributing to the successful development of numerous high-performance computing projects.

Provided expert consultancy services across eight technology firms, leading PDN design projects that resolved critical power integrity issues, resulting in enhanced product performance and market success.

Championed the adoption of advanced 2.5D and 3D packaging technologies, effectively overcoming PDN challenges and driving innovation in complex IC systems.

Pioneered the integration of Cadence® Sigrity™ PowerSI and PowerDC tools, leading to groundbreaking improvements in PDN design for high-performance computing systems.

Directed a team of engineers in the simulation and analysis of power delivery networks, achieving a 25% improvement in system efficiency and reliability through innovative design strategies.

Established new benchmarks for modeling voltage regulator switching ripple and transient response, enhancing the selection process for power stages, controllers, and passive components.

Provided expert consultancy on power integrity and PDN design, utilizing PowerSI and PowerDC to analyze and optimize numerous high-performance CPUs and compute SoCs for leading technology firms.

Implemented cutting-edge simulation techniques for PCB and package analysis, successfully resolving critical power and thermal management challenges.

Led Power Integrity (PI) projects from feasibility analysis to outcome presentation, emphasizing ROI and mitigating risk.

Specialized in optimizing computer architecture for enhanced machine learning application performance, focusing on ML hardware accelerators and non-volatile memory designs.

Led cross-functional teams to integrate high-speed PCIe interfaces, significantly improving data transfer reliability and system coherence.

Developed robust power integrity design review protocols, providing expert recommendations to meet stringent design specifications.

Automated design and post-processing flows using Python, TCL, and MATLAB, enhancing productivity by 40%.

Demonstrated proficiency with key EDA tools (VCS, Spyglass Lint, Questa CDC) to ensure accurate low-power design implementation.

Advocated and implemented low-power design principles, incorporating innovative clock gating techniques to achieve a notable 15% reduction in power consumption for key projects.

Employed cutting-edge EDA tools for the realization of power-efficient, high-speed computing architectures.

Developed high-accuracy, efficient algorithms for 3D computer vision models using OpenCV and TensorFlow.

Managed multiple GPU programming projects from conception to delivery, ensuring adherence to quality and performance standards.

Mentored junior GPU programmers, providing guidance on best practices and performance optimization techniques.

Implemented cutting-edge simulation techniques for PCB and package analysis, contributing to the successful resolution of critical power and thermal management challenges.

Led PI projects from feasibility analysis to outcome presentation, emphasizing ROI and risk management.

Specialized in optimizing computer architecture for enhanced machine learning application performance, focusing on ML hardware accelerators and non-volatile memory designs.

Designed end-to-end power delivery networks for digital and analog SoC domains, ensuring robust power supply from voltage regulators to on-chip decouplers.

Executed extensive PDN simulations to predict and mitigate issues like IR drop, current density, and thermal hotspots.

Utilized advanced 2.5D and 3D electromagnetic simulation tools to extract N-port models and generate accurate impedance profiles.

Employed scripting languages like Python, TCL, and MATLAB to automate design flows, enhancing efficiency and accuracy in data analysis for design improvements.

Orchestrated the design and optimization of PDN for various high-speed digital and analog SoC domains, leading to a 30% increase in system efficiency.

Pioneered modeling techniques to simulate voltage regulator ripple, bandwidth, and transient response, enhancing the power stage selection process.

Utilized 2.5D electromagnetic simulators for PCB and package modeling, extracting N-port models to develop comprehensive impedance profiles.

Executed time-domain simulations to characterize supply rail behaviors, effectively mitigating worst-case droops and overshoots.

Designed and verified IP components for high-performance computing applications, utilizing Verilog coding and advanced simulation tools to ensure optimal functionality and performance.

Played a pivotal role in designing and integrating high-speed PCIe interfaces, improving data transfer rates and system reliability.

Ensured compliance with AXI and APB interface protocols, maintaining system compatibility and interoperability.

Led cross-functional teams in the adoption of low-power design strategies, significantly reducing power consumption and contributing to eco-friendly product development.

Provided technical leadership and guidance to the team, fostering a culture of innovation and continuous learning.